LSI 53C810A - Manual (Page 151)

Block Move Instructions 6-11
3. The LSI53C810A compares the SCSI phase bits in
the DMA Command (DCMD) register with the latched
SCSI phase lines stored in the SCSI Status One
(SSTAT1) register. These phase lines are latched
when SREQ/ is asserted.
4. If the SCSI phase bits match the value stored in the
SCSI SCSI Status One (SSTAT1) register, the
LSI53C810A transfers the number of bytes specified
in the
DMA Byte Counter (DBC) register starting at
the address pointed to by the DMA Next Address
(DNAD) register.
5. If the SCSI phase bits do not match the value stored
in the SCSI Status One (SSTAT1) register, the
LSI53C810A generates a phase mismatch interrupt
and the instruction is not executed.
6. During a Message-Out phase, after the LSI53C810A
has performed a select with Attention (or SATN/ is
manually asserted with a Set ATN instruction), the
LSI53C810A deasserts SATN/ during the final
SREQ/SACK/ handshake of the first move of
Message-Out bytes after SATN/ was set.
7. When the LSI53C810A is performing a block move for
Message-In phase, it does not deassert the SACK/
signal for the last SREQ/SACK/ handshake. Clear the
SACK/ signal using the Clear SACK I/O instruction.
SCSIP[2:0] SCSI Phase [26:24]
This 3-bit field defines the desired SCSI information
transfer phase. When the LSI53C810A operates in
Initiator mode, these bits are compared with the latched
SCSI phase bits in the
SCSI Status One (SSTAT1)
register. When the LSI53C810A operates in Target mode,
the LSI53C810A asserts the phase defined in this field.
The following table describes the possible combinations
and the corresponding SCSI phase.