LSI 53C810A - Manual (Page 201)

PCI Interface Timing Diagrams 7-19
Figure 7.15 Back-to-Back Read
CLK
(Driven by System)
FRAME/
(Driven by LSI53C810A)
AD/
(Driven by LSI53C810A-
C_BE/
(Driven by LSI53C810A)
PAR
(Driven by LSI53C810A-
IRDY/
(Driven by LSI53C810A)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
Addr; Target-Data )
Addr; Target-Data)
GNT/
(Driven by Arbiter)
REQ/
(Driven by LSI53C810A)
GPIO1_MASTER/
(Driven by LSI53C810A)
GPIO0_FETCH/
(Driven by LSI53C810A )
In
CMD
t
9
Data In
In Out
t
6
t
5
t
3
t
4
t
3
t
3
t
3
t
3
t
1
t
2
t
2
t
1
t
2
t
1
t
2
t
10
t
1
Data In
Out
BE CMD BE
Addr
Out Addr
Out