LSI 53C810A - Manual (Page 38)

2-18 Functional Description
2.7.1.2 Fatal vs. Nonfatal Interrupts
A fatal interrupt, as the name implies, always causes SCRIPTS to stop
running. All nonfatal interrupts become fatal when they are enabled by
setting the appropriate interrupt enable bit. Interrupt masking is
discussed in
Section 2.7.1.3, “Masking.” All DMA interrupts (indicated by
the DIP bit in ISTAT and one or more bits in DSTAT being set) are fatal.
Some SCSI interrupts (indicated by the SIP bit in the Interrupt Status
(ISTAT) and one or more bits in SCSI Interrupt Status Zero (SIST0) or
SCSI Interrupt Status One (SIST1) being set) are nonfatal.
When the LSI53C810A is operating in the Initiator mode, only the
Function Complete (CMP), Selected (SEL), Reselected (RSL), General
Purpose Timer Expired (GEN), and Handshake to Handshake Timer
Expired (HTH) interrupts are nonfatal.
When operating in the Target mode, CMP, SEL, RSL, Target mode:
SATN/ active (M/A), GEN, and HTH are nonfatal. Refer to the description
for the Disable Halt on a Parity Error or SATN/ active (Target Mode Only)
(DHP) bit in the
SCSI Control One (SCNTL1) register to configure the
chip’s behavior when the SATN/ interrupt is enabled during Target mode
operation. The Interrupt-on-the-Fly interrupt is also nonfatal, since
SCRIPTS can continue when it occurs.
The reason for nonfatal interrupts is to prevent SCRIPTS from stopping
when an interrupt occurs that does not require service from the CPU.
This prevents an interrupt when arbitration is complete (CMP set), when
the LSI53C810A is selected or reselected (SEL or RSL set), when the
initiator asserts ATN (target mode: SATN/ active), or when the General
Purpose or Handshake-to-Handshake timers expire. These interrupts are
not needed for events that occur during high-level SCRIPTS operation.
2.7.1.3 Masking
Masking an interrupt means disabling or ignoring that interrupt. Interrupts
can be masked by clearing bits in the
SCSI Interrupt Enable Zero
(SIEN0) and SCSI Interrupt Enable One (SIEN1) (for SCSI interrupts)
registers or the DMA Interrupt Enable (DIEN) (for DMA interrupts)
register. How the chip responds to masked interrupts depends on: