LSI 53C810A - Manual (Page 136)

5-62 Operating Registers
Register: 0x4E (0xCE)
SCSI Test Two (STEST2)
Read/Write
SCE SCSI Control Enable 7
Setting this bit allows assertion of all SCSI control and
data lines through the
SCSI Output Control Latch (SOCL)
and SCSI Output Data Latch (SODL) registers regardless
of whether the LSI53C810A is configured as a target or
initiator.
Note: Do not set this bit during normal operation, since it could
cause contention on the SCSI bus. It is included for
diagnostic purposes only.
ROF Reset SCSI Offset 6
Setting this bit clears any outstanding synchronous
SREQ/SACK offset. Set this bit if a SCSI gross error
condition occurs and to clear the offset when a
synchronous transfer does not complete successfully.
The bit automatically clears itself after resetting the
synchronous offset.
R Reserved 5
SLB SCSI Loopback Mode 4
Setting this bit allows the LSI53C810A to perform SCSI
loopback diagnostics. That is, it enables the SCSI core to
simultaneously perform as both the initiator and the
target.
SZM SCSI High Impedance Mode 3
Setting this bit places all the open drain 48 mA SCSI
drivers into a high impedance state. This is to allow
internal loopback mode operation without affecting the
SCSI bus.
7 6 5 4 3 2 1 0
SCE ROF R SLB SZM R EXT LOW
0 0 x 0 0 x 0 0