LSI 53C810A - Manual (Page 29)

Parity Options 2-9
Asynchronous SCSI Send –
Step 1. Look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC)
registers and calculate if there are bytes left in the DMA FIFO.
To make this calculation, subtract the seven least significant bits
of the
DMA Byte Counter (DBC) register from the 7-bit value of
the DMA FIFO (DFIFO) register. AND the result with 0x7F for
a byte count between zero and 80.
Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) register to
determine if any bytes are left in the SCSI Output Data Latch
(SODL) register. If bit 5 is set in SSTAT0, then the SODL
register is full.
Synchronous SCSI Send –
Step 1. Look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC)
registers and calculate if there are bytes left in the DMA FIFO.
To make this calculation, subtract the seven least significant bits
of the
DMA Byte Counter (DBC) register from the 7-bit value of
the DMA FIFO (DFIFO) register. AND the result with 0x7F for
a byte count between zero and 80.
Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) register to
determine if any bytes are left in the SCSI Output Data Latch
(SODL) register. If bit 5 is set in SSTAT0, then the SCSI Output
Data Latch (SODL) register is full.
Step 3. Read bit 6 in the SCSI Status Zero (SSTAT0) register to
determine if any bytes are left in the SODR register. If bit 6 is
set in SSTAT0, then the SODR register is full.
Asynchronous SCSI Receive –
Step 1. Look at the DMA FIFO (DFIFO) and DMA Byte Counter (DBC)
registers and calculate if there are bytes left in the DMA FIFO.
To make this calculation, subtract the seven least significant bits
of the
DMA Byte Counter (DBC) register from the 7-bit value of
the DMA FIFO (DFIFO) register. AND the result with 0x7F for
a byte count between zero and 80.