LSI 53C810A User Manual
Page 97
5-23
OLF
SODL Full
5
This bit is set when
contains data. The
register is the interface between the DMA logic and the
SCSI bus. In synchronous mode, data is transferred from
the host bus to the
register, and then to the SCSI Output Data Register
(SODR, a hidden buffer register which is not accessible)
before being sent to the SCSI bus. In asynchronous
mode, data is transferred from the host bus to the
register, and then to the SCSI
bus. The SODR buffer register is not used for
asynchronous transfers. It is possible to use this bit to
determine how many bytes reside in the chip when an
error occurs.
AIP
Arbitration in Progress
4
Arbitration in Progress (AIP = 1) indicates that the
LSI53C810A has detected a Bus Free condition, asserted
BSY, and asserted its SCSI ID onto the SCSI bus.
LOA
Lost Arbitration
3
When set, LOA indicates that the LSI53C810A has
detected a bus free condition, arbitrated for the SCSI bus,
and lost arbitration due to another SCSI device asserting
the SEL/ signal.
WOA
Won Arbitration
2
When set, WOA indicates that the LSI53C810A has
detected a Bus Free condition, arbitrated for the SCSI
bus and won arbitration. The arbitration mode selected in
the
register must be full
arbitration and selection for this bit to be set.
RST/
SCSI RST/ Signal
1
This bit reports the current status of the SCSI RST/
signal, and the SRST signal (bit 6) in the
register.
SDP/
SCSI SDP/ Parity Signal
0
This bit represents the active high current status of the
SCSI SDP/ parity signal.