LSI 53C810A - Manual (Page 58)

3-16 PCI Functional Description
Register: 0x0C
Cache Line Size
Read/Write
CLS Cache Line Size [7:0]
This register specifies the system cache line size in units
of 32-bit words. Cache mode is enabled and disabled by
the Cache Line Size Enable (CLSE) bit, bit 7 in the
DMA
Control (DCNTL) register. Setting this bit causes the
LSI53C810A to align to cache line boundaries before
allowing any bursting, except during MMOVs in which the
read and write addresses are Burst Size boundary
misaligned. For more information see
Section 3.2.1,
“Support for PCI Cache Line Size Register,” page 3-3 .
Register: 0x0D
Latency Timer
Read/Write
LT Latency Timer [7:0]
The Latency Timer register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. The LSI53C810A supports this timer. All eight
bits are writable, allowing latency values of 0–255 PCI
clocks. Use the following equation to calculate an
optimum latency value for the LSI53C810A:
Latency = 2 + (Burst Size * (typical wait states +1))
Values greater than optimum are also acceptable.
7 0
CLS
0 0 0 0 0 0 0 0
7 0
LT
0 0 0 0 0 0 0 0