LSI 53C810A - Manual (Page 150)

6-10 Instruction Set of the I/O Processor
– If any other Group Code is received, the DMA Byte
Counter (DBC) register is not modified and the
LSI53C810A will request the number of bytes
specified in the
DMA Byte Counter (DBC) register.
If the DMA Byte Counter (DBC) register contains
0x000000, an illegal instruction interrupt is
generated.
4. The LSI53C810A transfers the number of bytes
specified in the DMA Byte Counter (DBC) register
starting at the address specified in the DMA Next
Address (DNAD) register.
5. If the SATN/ signal is asserted by the Initiator or a
parity error occurred during the transfer, the transfer
can optionally be halted and an interrupt generated.
The Disable Halt on Parity Error or ATN bit in the
SCSI Control One (SCNTL1) register controls
whether the LSI53C810A halts on these conditions
immediately, or waits until completion of the current
Move.
Initiator Mode
These instructions perform the following steps:
1. The LSI53C810A verifies that it is connected to the
SCSI bus as an Initiator before executing this
instruction.
2. The LSI53C810A waits for an unserviced phase to
occur. An unserviced phase is any phase (with SREQ/
asserted) for which the LSI53C810A has not yet
transferred data by responding with a SACK/.
OPC Instruction Defined
0 Reserved
1 MOVE