Figure6.7 load and store instruction format, Load and store instruction format – LSI 53C810A User Manual
Page 182
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6-42
Instruction Set of the I/O Processor
illustrates the register bit values that represent a Load and
Store instruction.
Figure 6.7
Load and Store Instruction Format
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8
7
6
5
4
3
2
1
0
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8
7
6
5
4
3
2
1
0
DSPS Register - Memory/ I/O Address/DSA Offset
DCMD Register
DBC Register
A0
A1
A2
A3
A4
A5
A6
0 (Reserved)
Load/Store
No Flush
0 - Reserved
0 - Reserved
DSA Relative
1
1
1
Register
Address
Instruction Type - Load and Store
Reserved
(must be 0)
Byte Count
(Number of bytes
to load/store)
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