Intel IA-32 - Manual (Page 120)

3-40 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
3.10.2 IA-32e Mode Linear Address Translation (2-MByte Pages)
Figure 3-25 shows the PML4 table, page-directory-pointer, and page-directory hierarchy when
mapping linear addresses to 2-MByte pages in IA-32e mode. This method can be used to address
up to 2
27 pages, which spans a linear address space of 2 48 bytes.
The 2-MByte page size is selected by setting the page size (PS) flag in a page-directory entry
(see Figure 3-14). The PSE flag in control register CR4 has no affect on the page size when PAE
is enabled. With the PS flag set, a linear address is divided into four sections:
•
PML4-table entry — Bits 47:39 provide an offset to an entry in the PML4 table. The
selected entry provides the base physical address of a page directory pointer table.
•
Page-directory-pointer-table entry — Bits 38:30 provide an offset to an entry in the
page-directory-pointer table. The selected entry provides the base physical address of a
page directory.
Figure 3-24. IA-32e Mode Paging Structures (4-KByte Pages)
Directory Ptr
Page-Table Entry
Linear Address
Page Table
Dir. Pointer Entry
CR3 (PML4)
39 38
Pointer Table
512 PML4 *512 PDPTE
∗ 512 PDE ∗ 512 PTE = 2 36
Pages
9
9
40 1
12
9
1. 40 bits aligned onto a 4-KByte boundary
28
4-KByte Page
Offset
Physical Addr
Directory Entry
Table
0 11 12 20 21
Directory
30 29
Page-Directory-
Page-Directory
PML4
47 48 63
Sign Extended
9
PML4 Entry
NOTES: