Intel IA-32 - Manual (Page 566)

15-16 Vol. 3A
8086 EMULATION
The method the processor uses to handle class 2 and 3 interrupts depends on the setting of the
following flags and fields:
•
IOPL field (bits 12 and 13 in the EFLAGS register) — Controls how class 3 software
interrupts are handled when the processor is in virtual-8086 mode (see Section 2.3,
“System Flags and Fields in the EFLAGS Register”). This field also controls the enabling
of the VIF and VIP flags in the EFLAGS register when the VME flag is set. The VIF and
VIP flags are provided to assist in the handling of class 2 maskable hardware interrupts.
•
VME flag (bit 0 in control register CR4) — Enables the virtual mode extension for the
processor when set (see Section 2.5, “Control Registers”).
•
Software interrupt redirection bit map (32 bytes in the TSS, see Figure 15-5) —
Contains 256 flags that indicates how class 3 software interrupts should be handled when
they occur in virtual-8086 mode. A software interrupt can be directed either to the interrupt
and exception handlers in the currently running 8086 program or to the protected-mode
interrupt and exception handlers.
•
The virtual interrupt flag (VIF) and virtual interrupt pending flag (VIP) in the
EFLAGS register — Provides virtual interrupt support for the handling of class 2
maskable hardware interrupts (see Section 15.3.2, “Class 2—Maskable Hardware Interrupt
Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism”).
NOTE
The VME flag, software interrupt redirection bit map, and VIF and VIP flags
are only available in IA-32 processors that support the virtual mode
extensions. These extensions were introduced in the IA-32 architecture with
the Pentium processor.
The following sections describe the actions that processor takes and the possible actions of inter-
rupt and exception handlers for the two classes of interrupts described in the previous para-
graphs. These sections describe three possible types of interrupt and exception handlers:
•
Protected-mode interrupt and exceptions handlers — These are the standard handlers
that the processor calls through the protected-mode IDT.
•
Virtual-8086 monitor interrupt and exception handlers — These handlers are resident
in the virtual-8086 monitor, and they are commonly accessed through a general-protection
exception (#GP, interrupt 13) that is directed to the protected-mode general-protection
exception handler.
•
8086 program interrupt and exception handlers — These handlers are part of the 8086
program that is running in virtual-8086 mode.
The following sections describe how these handlers are used, depending on the selected class
and method of interrupt and exception handling.
1. The INT 3 instruction is a special case (see the description of the INT n instruction in Chapter 3, “Instruc-
tion Set Reference, A-M”, of the IA-32 Intel® Architecture Software Developer’s Manual, Volume 2A).