Intel IA-32 - Manual (Page 27)

Vol. 3A xxvii
CONTENTS
PAGE
Figure 3-23. Format of Page-Directory Entries for 4-MByte Pages and
36-Bit Physical Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
Figure 3-24. IA-32e Mode Paging Structures (4-KByte Pages) . . . . . . . . . . . . . . . . . . . . 3-40
Figure 3-25. IA-32e Mode Paging Structures (2-MByte pages) . . . . . . . . . . . . . . . . . . . . 3-41
Figure 3-26. Format of Paging Structure Entries for 4-KByte Pages in IA-32e Mode . . . . 3-42
Figure 3-27. Format of Paging Structure Entries for 2-MByte Pages in IA-32e Mode. . . . 3-43
Figure 3-28. Memory Management Convention That Assigns a Page Table
to Each Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
Figure 4-1. Descriptor Fields Used for Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-2. Descriptor Fields with Flags used in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . 4-5
Figure 4-3. Protection Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Figure 4-4. Privilege Check for Data Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Figure 4-5. Examples of Accessing Data Segments From Various Privilege
Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Figure 4-6. Privilege Check for Control Transfer Without Using a Gate . . . . . . . . . . . . . 4-14
Figure 4-7. Examples of Accessing Conforming and Nonconforming Code
Segments From Various Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Figure 4-8. Call-Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Figure 4-9. Call-Gate Descriptor in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Figure 4-10. Call-Gate Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Figure 4-11. Privilege Check for Control Transfer with Call Gate . . . . . . . . . . . . . . . . . . . 4-21
Figure 4-12. Example of Accessing Call Gates At Various Privilege Levels . . . . . . . . . . . 4-23
Figure 4-13. Stack Switching During an Interprivilege-Level Call . . . . . . . . . . . . . . . . . . . 4-25
Figure 4-14. MSRs Used by SYSCALL and SYSRET . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Figure 4-15. Use of RPL to Weaken Privilege Level of Called Procedure . . . . . . . . . . . . 4-36
Figure 5-1. Relationship of the IDTR and IDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Figure 5-2. IDT Gate Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Figure 5-3. Interrupt Procedure Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5-4. Stack Usage on Transfers to Interrupt and Exception-Handling
Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Figure 5-5. Interrupt Task Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Figure 5-6. Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Figure 5-7. 64-Bit IDT Gate Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Figure 5-8. IA-32e Mode Stack Usage After Privilege Level Change . . . . . . . . . . . . . . . 5-25
Figure 5-9. Page-Fault Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
Figure 6-1. Structure of a Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Figure 6-2. 32-Bit Task-State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Figure 6-3. TSS Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Figure 6-4. Format of TSS and LDT Descriptors in 64-bit Mode . . . . . . . . . . . . . . . . . . . . 6-9
Figure 6-5. Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Figure 6-6. Task-Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Figure 6-7. Task Gates Referencing the Same Task . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Figure 6-8. Nested Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Figure 6-9. Overlapping Linear-to-Physical Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Figure 6-10. 16-Bit TSS Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Figure 6-11. 64-Bit TSS Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Figure 7-1. Example of Write Ordering in Multiple-Processor Systems . . . . . . . . . . . . . 7-10
Figure 7-2. Interpretation of APIC ID in Early MP Systems. . . . . . . . . . . . . . . . . . . . . . . 7-23
Figure 7-3. Local APICs and I/O APIC in MP System Supporting HT Technology . . . . . 7-26
Figure 7-4. IA-32 Processor with Two Logical Processors Supporting HT
Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Figure 7-5. Generalized Four level Interpretation of the initial APIC ID. . . . . . . . . . . . . . 7-36