Intel IA-32 - Manual (Page 32)

CONTENTS
xxxii Vol. 3A
PAGE
Table 11-3. Effect of the MMX, x87 FPU, and FXSAVE/FXRSTOR Instructions
on the x87 FPU Tag Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Table 12-1. Action Taken for Combinations of OSFXSR, OSXMMEXCPT, SSE,
SSE2, SSE3, EM, MP, and TS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Table 13-1. On-Demand Clock Modulation Duty Cycle Field Encoding . . . . . . . . . . . . . . 13-7
Table 14-1. Extended Machine Check State MSRs in Processors Without Support
for EM64T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Table 14-2. Extended Machine Check State MSRs
In Processors With Support For Intel EM64T . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Table 14-3. IA32_MCi_Status [15:0] Simple Error Code Encoding . . . . . . . . . . . . . . . . .14-14
Table 14-4. IA32_MCi_Status [15:0] Compound Error Code Encoding. . . . . . . . . . . . . .14-15
Table 14-5. Encoding for TT (Transaction Type) Sub-Field. . . . . . . . . . . . . . . . . . . . . . .14-15
Table 14-6. Level Encoding for LL (Memory Hierarchy Level) Sub-Field . . . . . . . . . . . .14-15
Table 14-7. Encoding of Request (RRRR) Sub-Field . . . . . . . . . . . . . . . . . . . . . . . . . . .14-16
Table 14-8. Encodings of PP, T, and II Sub-Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-17
Table 15-1. Real-Address Mode Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . 15-8
Table 15-2. Software Interrupt Handling Methods While in Virtual-8086 Mode . . . . . . . .15-24
Table 16-1. Characteristics of 16-Bit and 32-Bit Program Modules. . . . . . . . . . . . . . . . . . 16-1
Table 17-1. New Instruction in the Pentium Processor and Later IA-32
Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
Table 17-2. Recommended Values of the EM, MP, and NE Flags for Intel486 SX
Microprocessor/Intel 487 SX Math Coprocessor System . . . . . . . . . . . . . . .17-20
Table 17-3. EM and MP Flag Interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-20
Table 18-1. Breakpointing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
Table 18-2. Debug Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
Table 18-3. LBR MSR Stack Structure for the Pentium 4 and Intel Xeon
Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-14
Table 18-4. MSR_DEBUGCTLA MSR Flag Encodings . . . . . . . . . . . . . . . . . . . . . . . . . .18-21
Table 18-5. CPL-Qualified Branch Trace Store Encodings . . . . . . . . . . . . . . . . . . . . . . .18-22
Table 18-6. Performance Counter MSRs and Associated CCCR and
ESCR MSRs (Pentium 4 and Intel Xeon Processors) . . . . . . . . . . . . . . . . .18-31
Table 18-7. Event Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-45
Table 18-8. CCR Names and Bit Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-50
Table 18-9. Effect of Logical Processor and CPL Qualification for Logical
Processor-Specific (TS) Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-65
Table 18-10. Effect of Logical Processor and CPL Qualification for
Non-logical-processor-specific (TI) Events . . . . . . . . . . . . . . . . . . . . . . . . . .18-65
Table 20-1. Format of the VMCS Region. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
Table 20-2. Format of Access Rights. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
Table 20-3. Format of Interruptibility State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Table 20-4. Format of Pending-Debug-Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
Table 20-5. Definitions of Pin-Based VM-Execution Controls . . . . . . . . . . . . . . . . . . . . . . 20-9
Table 20-6. Definitions of Processor-Based VM-Execution Controls. . . . . . . . . . . . . . . .20-10
Table 20-7. Definitions of VM-Exit Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-14
Table 20-8. Format of an MSR Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-15
Table 20-9. Definitions of VM-Entry Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-16
Table 20-10. Format of the VM-Entry Interruption-Information Field . . . . . . . . . . . . . . . . .20-17
Table 20-11. Format of Exit Reason . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-18
Table 20-12. Format of the VM-Exit Interruption-Information Field . . . . . . . . . . . . . . . . . .20-19
Table 20-13. Format of the IDT-Vectoring Information Field . . . . . . . . . . . . . . . . . . . . . . .20-20
Table 20-14. Format of the VMX-Instruction Information Field . . . . . . . . . . . . . . . . . . . . .20-21
Table 20-15. Structure of VMCS Component Encoding . . . . . . . . . . . . . . . . . . . . . . . . . .20-24