Intel IA-32 - Manual (Page 618)

17-26 Vol. 3A
IA-32 ARCHITECTURE COMPATIBILITY
tecture has been added for handling and reporting on hardware errors. See Chapter 14,
“Machine-Check Architecture,” for a detailed description of the new conditions.
The following exceptions and/or exception conditions were added to the IA-32 with the Pentium
processor:
•
Machine-check exception (#MC, interrupt 18) — New exception. This exception reports
parity and other hardware errors. It is a model-specific exception and may not be
implemented or implemented differently in future processors. The MCE flag in control
register CR4 enables the machine-check exception. When this bit is clear (which it is at
reset), the processor inhibits generation of the machine-check exception.
•
General-protection exception (#GP, interrupt 13) — New exception condition added. An
attempt to write a 1 to a reserved bit position of a special register causes a general-
protection exception to be generated.
•
Page-fault exception (#PF, interrupt 14) — New exception condition added. When a 1 is
detected in any of the reserved bit positions of a page-table entry, page-directory entry, or
page-directory pointer during address translation, a page-fault exception is generated.
The following exception was added to the Intel486 processor:
•
Alignment-check exception (#AC, interrupt 17) — New exception. Reports unaligned
memory references when alignment checking is being performed.
The following exceptions and/or exception conditions were added to the Intel386 processor:
•
Divide-error exception (#DE, interrupt 0)
— Change in exception handling. Divide-error exceptions on the Intel386 processors
always leave the saved CS:IP value pointing to the instruction that failed. On the 8086
processor, the CS:IP value points to the next instruction.
— Change in exception handling. The Intel386 processors can generate the largest
negative number as a quotient for the IDIV instruction (80H and 8000H). The 8086
processor generates a divide-error exception instead.
•
Invalid-opcode exception (#UD, interrupt 6) — New exception condition added. Improper
use of the LOCK instruction prefix can generate an invalid-opcode exception.
•
Page-fault exception (#PF, interrupt 14) — New exception condition added. If paging is
enabled in a 16-bit program, a page-fault exception can be generated as follows. Paging
can be used in a system with 16-bit tasks if all tasks use the same page directory. Because
there is no place in a 16-bit TSS to store the PDBR register, switching to a 16-bit task does
not change the value of the PDBR register. Tasks ported from the Intel 286 processor
should be given 32-bit TSSs so they can make full use of paging.
•
General-protection exception (#GP, interrupt 13) — New exception condition added. The
Intel386 processor sets a limit of 15 bytes on instruction length. The only way to violate
this limit is by putting redundant prefixes before an instruction. A general-protection
exception is generated if the limit on instruction length is violated. The 8086 processor has
no instruction length limit.