See table 8-1) and – Intel IA-32 User Manual

Page 332

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8-8 Vol. 3A

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

Table 8-1 shows how the APIC registers are mapped into the 4-KByte APIC register space.
Registers are 32 bits, 64 bits, or 256 bits in width; all are aligned on 128-bit boundaries. All
32-bit registers should be accessed using 128-bit aligned 32-bit loads or stores. Some processors
may support loads and stores of less than 32 bits to some of the APIC registers. This is model
specific behavior and is not guaranteed to work on all processors. Wider registers (64-bit or 256-
bit) must be accessed using multiple 32-bit loads or stores, with the first access being 128-bit
aligned. If a LOCK prefix is used with a MOV instruction that accesses the APIC address space,
the prefix is ignored. The locking operation does not take place. All the registers listed in Table
8-1 are described in
the following sections.

The local APIC registers listed in Table 8-1 are not MSRs. The only MSR associated with the
programming of the local APIC is the IA32_APIC_BASE MSR (see Section 8.4.3, “Enabling
or Disabling the Local APIC”)
.

Table 8-1. Local APIC Register Address Map

Address

Register Name

Software Read/Write

FEE0 0000H

Reserved

FEE0 0010H

Reserved

FEE0 0020H

Local APIC ID Register

Read/Write.

FEE0 0030H

Local APIC Version Register

Read Only.

FEE0 0040H

Reserved

FEE0 0050H

Reserved

FEE0 0060H

Reserved

FEE0 0070H

Reserved

FEE0 0080H

Task Priority Register (TPR)

Read/Write.

FEE0 0090H

Arbitration Priority Register

1

(APR)

Read Only.

FEE0 00A0H

Processor Priority Register (PPR)

Read Only.

FEE0 00B0H

EOI Register

Write Only.

FEE0 00C0H

Reserved

FEE0 00D0H

Logical Destination Register

Read/Write.

FEE0 00E0H

Destination Format Register

Bits 0-27 Read only; bits 28-31
Read/Write.

FEE0 00F0H

Spurious Interrupt Vector Register

Bits 0-8 Read/Write; bits 9-31
Read Only.

FEE0 0100H through
FEE0 0170H

In-Service Register (ISR)

Read Only.

FEE0 0180H through
FEE0 01F0H

Trigger Mode Register (TMR)

Read Only.

FEE0 0200H through
FEE0 0270H

Interrupt Request Register (IRR)

Read Only.

FEE0 0280H

Error Status Register

Read Only.

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