Intel IA-32 - Manual (Page 39)

Vol. 3A 1-3
ABOUT THIS MANUAL
level, including: task switching, exception handling, and compatibility with existing system
environments.
Chapter 12 — SSE, SSE2 and SSE3 System Programming. Describes those aspects of
SSE/SSE2/SSE3 extensions that must be handled and considered at the system programming
level, including task switching, exception handling, and compatibility with existing system
environments.
Chapter 13 — Power and Thermal Management. Describes the IA-32 architecture’s power
and the thermal monitoring facilities.
Chapter 14 — Machine-Check Architecture. Describes the machine-check architecture.
Chapter 15 — 8086 Emulation. Describes the real-address and virtual-8086 modes of the
IA-32 architecture.
Chapter 16 — Mixing 16-Bit and 32-Bit Code. Describes how to mix 16-bit and 32-bit code
modules within the same program or task.
Chapter 17 — IA-32 Architecture Compatibility. Describes architectural compatibility
among the IA-32 processors, which include the Intel 286, Intel386™, Intel486™, Pentium, P6
family, Pentium 4, and Intel Xeon processors. The differences among the 32-bit IA-32 proces-
sors are also described throughout the three volumes of the IA-32 Software Developer’s
Manual, as relevant to particular features of the architecture. This chapter provides a collection
of all the relevant compatibility information for all IA-32 processors and also describes the basic
differences with respect to the 16-bit IA-32 processors (the Intel 8086 and Intel 286 processors).
Chapter 18 — Debugging and Performance Monitoring. Describes the debugging registers
and other debug mechanism provided in the IA-32 architecture. This chapter also describes the
time-stamp counter and the performance-monitoring counters.
Chapter 19 — Introduction to Virtual-Machine Extensions. Describes the basic elements of
virtual machine architecture and the virtual-machine extensions of IA-32 Intel Architecture..
Chapter 20 — Virtual-Machine Control Structures. Describes components that manage
VMX operation. These include the working-VMCS pointer and the controlling-VMCS pointer.
Chapter 21— VMX Non-Root Operation. Describes the operation of a VMX non-root oper-
ation. Processor operation in VMX non-root mode can be restricted programmatically such that
certain operations, events or conditions can cause the processor to transfer control from the guest
(running in VMX non-root mode) to the monitor software (running in VMX root mode).
Chapter 22 — VM Entries. Describes VM-entries. VM-entry transitions the processor from
the VMM running in VMX root-mode to a VM running in VMX non-root mode. VM-Entry is
performed by the execution of VMLAUNCH or VMRESUME instructions.
Chapter 23 — VM Exits. Describes VM-exits. Certain events, operations or situations while
the processor is in VMX non-root operation may cause VM-exit transitions. In addition VM-
exits can also occur on failed VM-entries.
Chapter 24 — System Management. Describes the IA-32 architecture’s system management
mode (SMM) facilities.