Intel IA-32 - Manual (Page 442)

10-2 Vol. 3A
MEMORY CACHE CONTROL
Table 10-1. Characteristics of the Caches, TLBs, Store Buffer, and
Write Combining Buffer in IA-32 Processors
Cache or Buffer Characteristics
Trace Cache 1 - Pentium 4 and Intel Xeon processors: 12 K
μops, 8-way set associative.
- Pentium M processor: not implemented.
- P6 family and Pentium processors: not implemented.
L1 Instruction Cache - Pentium 4 and Intel Xeon processors: not implemented.
- Pentium M processor: 32-KByte, 8-way set associative.
- P6 family and Pentium processors: 8- or 16-KByte, 4-way set associative,
32-byte cache line size; 2-way set associative for earlier Pentium processors.
L1 Data Cache - Pentium 4 and Intel Xeon processors: 8-KByte, 4-way set associative, 64-byte
cache line size.
- Pentium 4 and Intel Xeon processors: 16-KByte, 8-way set associative, 64-byte
cache line size.
- Pentium M processor: 32-KByte, 8-way set associative, 64-byte cache line size.
- P6 family processors: 16-KByte, 4-way set associative, 32-byte cache line size;
8-KBytes, 2-way set associative for earlier P6 family processors.
- Pentium processors: 16-KByte, 4-way set associative, 32-byte cache line size;
8-KByte, 2-way set associative for earlier Pentium processors.
L2 Unified Cache - Pentium 4 and Intel Xeon processors: 256, 512, 1024, or 2048-KByte, 8-way set
associative, 64-byte cache line size, 128-byte sector size.
- Pentium M processor: 1 or 2-MByte, 8-way set associative, 64-byte cache line
size.
- P6 family processors: 128-KByte, 256-KByte, 512-KByte, 1-MByte, or 2-MByte,
4-way set associative, 32-byte cache line size.
- Pentium processor (external optional): System specific, typically 256- or
512-KByte, 4-way set associative, 32-byte cache line size.
L3 Unified Cache - Intel Xeon processors: 512-KByte, 1-MByte, 2-MByte, or 4-MByte, 8-way set
associative, 64-byte cache line size, 128-byte sector size.
Instruction TLB
(4-KByte Pages) - Pentium 4 and Intel Xeon processors: 128 entries, 4-way set associative.
- Pentium M processor: 128 entries, 4-way set associative.
- P6 family processors: 32 entries, 4-way set associative.
- Pentium processor: 32 entries, 4-way set associative; fully set associative for
Pentium processors with MMX technology.
Data TLB (4-KByte
Pages) - Pentium 4 and Intel Xeon processors: 64 entries, fully set associative; shared
with large page data TLBs.
- Pentium M processor: 128 entries, 4-way set associative.
- Pentium and P6 family processors: 64 entries, 4-way set associative; fully set.
associative for Pentium processors with MMX technology.
Instruction TLB
(Large Pages) - Pentium 4 and Intel Xeon processors: large pages are fragmented.
- Pentium M processor: 2 entries, fully associative.
- P6 family processors: 2 entries, fully associative.
- Pentium processor: Uses same TLB as used for 4-KByte pages.
Data TLB (Large
Pages) - Pentium 4 and Intel Xeon processors: 64 entries, fully set associative; shared
with small page data TLBs.
- Pentium M processor: 8 entries, fully associative.
- P6 family processors: 8 entries, 4-way set associative.
- Pentium processor: 8 entries, 4-way set associative; uses same TLB as used for
4-KByte pages in Pentium processors with MMX technology.