Intel IA-32 - Manual (Page 495)

Vol. 3A 11-7
INTEL® MMX™ TECHNOLOGY SYSTEM PROGRAMMING
Figure 11-2. Mapping of MMX Registers to x87 FPU Data Register Stack
MM0
MM1
MM2
MM3
MM4
MM5
MM6
MM7
ST1
ST2
ST7
ST0 ST6
ST7
ST1
TOS
TOS
x87 FPU “push” x87 FPU “pop”
x87 FPU “push”
x87 FPU “pop”
Case A: TOS=0
Case B: TOS=2
MM0
MM1
MM2
MM3
MM4
MM5
MM6
MM7
ST0
Outer circle = x87 FPU data register’s logical location relative to TOS
Inner circle = x87 FPU tags = MMX register’s location = FP registers’s physical location
(R0)
(R2)
(R2)
(R0)