Renesas Emulation Pod M306N4T3-RPD-E - Manual (Page 55)

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Vcc1 = Vcc2 = 5 V
5.2 Operation Timing in Memory Expansion and Microprocessor Modes (5 V)
(1) Separate Bus Timing
Table 5.2 and Figure 5.1 show the bus timing in memory expansion and microprocessor modes (3-
wait, accessing external area).
Table 5.2 Memory expansion and microprocessor modes (3-wait, accessing external area)
*1 Calculated by the following formula according to the frequency of BCLK.
*2 Calculated by the following formula according to the frequency of BCLK.
-40 [ns] n: "3" for 3-wait
( n - 0.5)x10 9
f (BCLK)
0.5x10 9
f (BCLK)
[ns]
Symbol Item
Actual MCU
[ns]
This product
[ns]
Min.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Min. Max.
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select output delay time
Chip-select output hold time (BCLK standard)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
4
0
(*2)
4
-4
0
0
4
(*1)
(*2)
25
25
25
25
25
40
See left
See left
(*3)
See left
See left
See left
See left
See left
See left
See left
Max.
See left
See left
See left
See left
See left
See left
*3 Calculated by the following formula according to the frequency of BCLK.
0.5x10 9
f (BCLK)
-4 [ns]