Texas Instruments TMS320C6454 - Manual (Page 141)

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PRODUCT PREVIEW
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
7.8.3.1 PLL Controller Divider 1 Register
The PLL controller divider 1 register (PLLDIV1) is shown in Figure 7-24 and described in Table 7-33 .
31 16
Reserved
R-0
15 14 5 4 0
D1EN Reserved RATIO
R/W-1 R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-24. PLL Controller Divider 1 Register (PLLDIV1) [Hex Address: 029C 0118]
Table 7-33. PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
Bit Field Value Description
31:16 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
15 D1EN Divider D1 enable bit.
0 Divider D1 is disabled. No clock output.
1 Divider D1 is enabled.
14:5 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
4:0 RATIO 0-1Fh Divider ratio bits.
1h ÷2. Divide frequency by 2.
4h ÷5. Divide frequency by 5.
Others Reserved
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