Figure 2-12, Product preview – Texas Instruments TMS320C6454 User Manual
Page 48
www.ti.com
PRODUCT PREVIEW
C64x+
t
DSP:
C6454
PREFIX
TMX
320
C6454
ZTZ
TMX = Experimental device
TMS = Qualified device
DEVICE FAMILY
320 = TMS320
t
DSP family
PACKAGE TYPE
(A)
ZTZ = 697-pin plastic BGA, with Pb-Free solder balls
GTZ = 697-pin plastic BGA, with Pb-ed solder balls
DEVICE
A. BGA = Ball Grid Array
DEVICE SPEED RANGE
7 = 720 MHz
8 = 850 MHz
Blank = 1 GHz
( )
TEMPERATURE RANGE
Blank = 0
°
C to +90
°
C (default commercial temperature)
( )
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZTZ), the temperature range (for example, blank is the default commercial
temperature range), and the device speed range, in megahertz (for example, blank is 1000 MHz [1 GHz]).
provides a legend for reading the complete device name for any TMS320C64x+™ DSP
generation member.
For device part numbers and further ordering information for TMS320C6454 in the ZTZ/GTZ package
type, see the TI website (
) or contact your TI sales representative.
Figure 2-12. TMS320C64x+™ DSP Device Nomenclature (including the TMS320C6454 DSP)
2.8.2.2
Documentation Support
The following documents describe the TMS320C6454 Fixed-Point Digital Signal Processor. Copies of
these documents are available on the Internet at
. Tip: Enter the literature number in the
search box provided at www.ti.com.
The current documentation that describes the TMS320C6454, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at:
www.ti.com/c6000
.
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+
digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP
generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an
enhancement of the C64x DSP with added functionality and an expanded instruction set.
TMS320C64x+ DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the
TMS320C64x+ digital signal processor (DSP) of the TMS320C6000 DSP family can be
efficiently used in DSP applications. Shows how to maintain coherence with external
memory, how to use DMA to reduce memory latencies, and how to optimize your code to
improve cache efficiency. The internal memory architecture in the C64x+ DSP is organized
in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data
cache (L1D) on the first level. Accesses by the CPU to the these first level caches can
complete without CPU pipeline stalls. If the data requested by the CPU is not contained in
cache, it is fetched from the next lower memory level, L2 or external memory.
TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas
Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
Device Overview
48