Texas Instruments TMS320C6454 - Manual (Page 152)

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PRODUCT PREVIEW
4
5
1
2
AECLKIN
AECLKOUT1
3 3
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the
EMIFA Module
(1) (2) (3)
(see Figure 7-32 )
-720
-850
NO. PARAMETER UNIT
-1000
MIN MAX
1 t
c(EKO)
Cycle time, AECLKOUT E – 0.7 E + 0.7 ns
2 t
w(EKOH)
Pulse duration, AECLKOUT high EH – 0.7 EH + 0.7 ns
3 t
w(EKOL)
Pulse duration, AECLKOUT low EL – 0.7 EL + 0.7 ns
4 t
t(EKO)
Transition time, AECLKOUT 1 ns
5 t
d(EKIH-EKOH)
Delay time, AECLKIN high to AECLKOUT high 1 8 ns
6 t
d(EKIL-EKOL)
Delay time, AECLKIN low to AECLKOUT low 1 8 ns
(1) E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.
(2) The reference points for the rise and fall transitions are measured at V
OL
MAX and V
OH
MIN.
(3) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
Figure 7-32. AECLKOUT Timing for the EMIFA Module
7.10.3.1 Asynchronous Memory Timing
Table 7-44. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module
(1) (2) (3)
(see Figure 7-33 and Figure 7-34 )
-720
-850
NO. UNIT
-1000
MIN MAX
3 t
su(EDV-AOEH)
Setup time, AEDx valid before AAOE high 6.5 ns
4 t
h(AOEH-EDV)
Hold time, AEDx valid after AAOE high 3 ns
5 t
su(ARDY-EKOH)
Setup time, AARDY valid before AECLKOUT low 1 ns
6 t
h(EKOH-ARDY)
Hold time, AARDY valid after AECLKOUT low 2 ns
7 t
w(ARDY)
Pulse width, AARDY assertion and deassertion 2E + 5 ns
Delay time, from AARDY sampled deasserted on AECLKOUT falling to
8 t
d(ARDY-HOLD)
4E ns
beginning of programmed hold period
Setup time, before end of programmed strobe period by which AARDY
9 t
su(ARDY-HOLD)
2E ns
should be asserted in order to insert extended strobe wait states.
(1) E = AECLKOUT period in ns for EMIFA
(2) To ensure data setup time, simply program the strobe width wide enough.
(3) AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E
to ensure setup and hold time is met.
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