Texas Instruments TMS320C6454 - Manual (Page 144)

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PRODUCT PREVIEW
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
7.8.3.5 PLLDIV Ratio Change Status Register
Whenever a different ratio is written to the PLLDIV1 register, the PLLCTRL flags the change in the
DCHANGE status register. During the GO operation, the PLL controller will only change the divide ratio
SYSCLK1 if SYS1 in DCHANGE is 1. The PLLDIV divider ratio change status register is shown in
Figure 7-28 and described in Table 7-37 .
31 16
Reserved
R-0
15 1 0
Reserved SYS1
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-28. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029C 0144]
Table 7-37. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit Field Value Description
31:1 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0 SYS1 SYSCLK1 divide ratio has been modified. SYSCLK1 ratio will be modified during GO operation.
0 SYSCLK1 ratio has not been modified. When GOSET is set, SYSCLK1 will not be affected.
1 SYSCLK1 ratio has been modified. When GOSET is set, SYSCLK1 will change to the new ratio.
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