Texas Instruments TMS320C6454 - Manual (Page 142)

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PRODUCT PREVIEW
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
7.8.3.2 PLL Controller Command Register
The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is
shown in
Figure 7-25 and described in Table 7-34 .
31 16
Reserved
R-0
15 2 1 0
Reserved Rsvd GOSET
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-25. PLL Controller Command Register (PLLCMD) [Hex Address: 029C 0138]
Table 7-34. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit Field Value Description
31:2 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
1 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0 GOSET GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1
to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous
GO operations have completed.
0 No effect. Write of 0 clears bit to 0.
1 Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further
writes of 1 can initiate the GO operation.
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