Rockwell Automation 1794-VHSC 1794 FLEX I/O Very High Speed Counter Module User Manual - Manual (Page 46)

38 Rockwell Automation Publication 1794-UM010D-EN-E - July 2013
Communicate With Your Module
Word 8 Module Channel Status Word
00 Zero input status bit (ZS) for Channel 0 – This bit represents
the present status of the Z input.
0 = Off
1 = Input on
This bit is uneffected by Z invert, ZI, in the counter configuration word.
01 Zero frequency detected bit (ZF) for Channel 0 – Only used during
frequency configurations (period/rate, continuous/rate, and rate
measurement). In period/rate and continuous/rate, counts are acquired
during on state of the Z input. At very low frequencies, the counter
saturates, indicating a zero frequency detect. The time it takes to
determine a zero frequency in these 2 configurations can be as long as
6.7 s (16,777,215 counts X 1/5 MHz X 2 half cycles of Z). In rate
measurement, pulses on Z are counted over a sample interval specified
by the product of time base X gate interval.
The time to detect a zero frequency is determined by the sample
interval
example: time base = 0.100s, gate interval = 3 is 300 ms to
determine ZF.
02, 03 Stored/data count bit (C0, C1) for Channel 0 – This count cycles thru
00, 01, 10, 11, 00... Each time the stored/accumulated count words are
updated, C(0,1) is incremented. The PLC sample rate, including network
delay and program scan, must be as fast or faster than the frequency of
the event which updates.
04 Zero input status bit (ZS) for Channel 1 – This bit represents
the present status of the Z input.
0 = Off
1 = Input on
05 Zero frequency detected bit (ZF) for Channel 1 – Only used during
frequency configurations (period/rate, continuous/rate, and rate
measurement). In period/rate and continuous/rate, counts are acquired
during on state of the Z input. At very low frequencies, the counter
saturates, indicating a zero frequency detect. The time it takes to
determine a zero frequency in these 2 configurations can be as long as
6.7 s (16,777,215 counts X 1/5 MHz X 2 half cycles of Z). In rate
measurement, pulses on Z are counted over a sample interval specified
by the product of time base X gate interval.
The time to detect a zero frequency is determined by the
sample interval
example: time base = 0.100 s, gate interval = 3 is 300 ms to
determine ZF.
06, 07 Stored/data count bit (C0, C1) for Channel 1 – This count cycles
through 00, 01, 10, 11, 00... Each time the stored/accumulated count
words are updated, C(0,1) is incremented. The PLC sample rate,
including network delay and program scan, must be as fast or faster
than the frequency of the event which updates.
08…11
(10…13) Output status indicators (OS) – Bit 08 corresponds to output 0, bit 09
to output 1, bit 10 to output 2, and bit 11 to output 3.
0 = output Off
1 = output On
Bit/Word Definitions
Input Word Bit Definition