ADLINK PXI-2022 - Manual (Page 12)

4 Introduction
Triggers
Trigger Specifications
Model Name PXI-2020/2022
Trigger Sources
(refer to section 4.4 for details)
(1)Software
(2)AFI [0..7]
(3)PXI Star Trigger
(4)PXI Trigger Bus[5] (SSI)
(5)SMB Trigger I/O (please refer to chapter
2.3 for details)
*GA 3-8 can use (1), (2), (4), (5) as output
signals. GA2 can use all options.
Trigger Mode
Pre-Trigger, Post-Trigger, Middle-Trigger,
Delay-Trigger
AFI (Auxiliary Function Interface)
Number of Channel 8 input/output (refer to pin legend definition)
Compatibility Output 3.3 V TTL
Input Logic Levels
Input low voltage: 0.8 V (max)
Input high voltage: 2.0 V(min)
Output Logic Levels
Output low voltage: 0.4 V (max)
Output high voltage: 2.8 V (min)
Output Driving Capacity ±24 mA
Maximum Input Overload -0.5 V to +5.5 V
Trigger Condition Rising or Falling, software selectable
Minimum Pulse Width 12.5 ns
Power-on State Input, pull-low with 10KΩ resistor
Data Transfer Polling mode
PXI Star Trigger
Receive Trigger from PXI Star Trigger
Compatibility Output 3.3 V TTL
Pulse Duration 12.5 ns
Pulse Logic Rising or Falling edge, software selectable
PXI Trigger Bus[0..7]
Receive Trigger from PXI Trigger Bus line 5
Compatibility
Input 3.3 V or 5 V TTL
Output 3.3 V TTL
Pulse Duration 12.5 ns
Pulse Logic Rising or Falling edge, software selectable
Table 1-2: Triggers