ADLINK PXI-2022 - Manual (Page 49)

Function Block and Operation Theory 41
The 3 internal timing signals could be routed to the PXI trigger bus
through software drivers. Please refer to section 4.6.1 for detailed
information of the 6 internal timing signals. Physically the signal
routings are accomplished in the FPGA. Cards that are connected
together through the PXI trigger bus, will still achieve synchroniza-
tion on the 3 timing signals.
Figure 4-15: SSI Mode Operation
4.7.1 SSI_TIMEBASE
As an output, the SSI_TIMEBASE signal outputs the onboard
LVTTL time-base through PXI trigger bus line 0. As an input, the
PXI-2020/2022 accepts the SSI_TIMEBASE signal to be the
source of timebase.
In PXI form factor, we utilize the PXI trigger bus built on the PXI
backplane to provide the necessary timing signal connections. All
the SSI signals are routed to the J2 connector. No additional cable
is needed. For detailed information of the PXI specifications,
please refer to PXI specification Revision 2.0 from PXI System
Alliance (www.pxisa.org).
SSI_AD_CONV
SSI_AD_TRG
SSI_SCAN_START
SSI_TIMEBASE
PX
I Interf
ace
PXI Trigger
Bus[0:7]
Timing Control
Trigger Bus[0]
Trigger Bus[1]
Trigger Bus[5]
Trigger Bus[3]
SSI_ADCONV
SSI_AD_TRIG
SSI_SCAN_ST
ART