ADLINK PXI-2022 - Manual (Page 42)

34 Function Block and Operation Theory
4.5 User-controllable Timing Signals
In order to meet the requirements for user-specific timing and the
re-quirements for synchronizing multiple cards, the PXI-2020/2022
series provides flexible user-controllable timing signals to connect
to external circuitry or additional cards.
The entire DAQ timing of the PXI-2020/2022 series is composed
of a bunch of counters and trigger signals in the FPGA. These tim-
ing signals are related to the A/D conversions and Timer/Counter
applications. These timing signals can be inputs to or outputs from
the I/O connectors, the SSI connector and the PXI bus. Therefore
the internal timing signals can be used to control external devices
or circuitry’s. However, the SSI/PXI timing signals remain the
same for every PXI-2020/2022 card.
We implemented signal multiplexers in the FPGA to individually
choose the desired timing signals for the DAQ operations, as
shown in the Figure 4-9.
Figure 4-9: DAQ Signal Routing
You can utilize the flexible timing signals through our software driv-
ers, and simply and correctly connect the signals with the PXI-
2020/2022 series cards. Here is the summary of the DAQ timing
signals and the corresponding functionalities for PXI-2020/2022
series.
To route an internal signal to the AFIn, PXI STAR Trigger, or the
PXI Trigger Bus[5] line, or to enable clock sharing through the PXI
trigger bus line or the PXI Star trigger line. please refer to D2K-
DASK Function Reference, check the D2K-Route_Siganl Usage
for details.
Internal timing
signals
SSI timing
Signals
AFI timing
signals
DAQ timing
signals
SSI timing
Signals
Trigger_Out
timing signals