ADLINK PXI-2022 - Manual (Page 31)

Function Block and Operation Theory 23
4 Function Block and Operation Theory
The operation theory of the functions on the PXI-2020/2022 is
described in this chapter. The functions include the A/D conver-
sion, Digital I/O and General Purpose Counter/Timer. The opera-
tion theory can help you understand how to configure and program
the PXI-2020/2022.
The entire PXI-2020 series of cards includs the PXI-2020/2022. In
the PXI-2022 cards, all the A/D related timings are for simultane-
ously A/D sampling based on scanning, so that PXI-2022 also
adopts the same concept, except there is only one conversion sig-
nal in a scan which could generate up to 16 samples from the dif-
ferent 16 channels at the same time. In the following description,
to conform to the original timing design, we still use “scan” as the
unit of A/D data acquisition.
4.1 Overall Function Block Diagram
Figure 4-1: PXI-2022 Functional Block Diagram
SCSI
CON
N
E
CTOR
X 2
INT
E
R
F
A
C
E
PXI I
N
T
E
R
F
A
C
E
AI Configure
/Calibration
Control
Analog Input
Timing Control
FPGA
Analog Input
Trigger
Control
Counter/Timing
Control
PXI
INTERFACE
EEPROM
Calibration
Data Storage
AI DATA
SPI Control
Inp
u
t G
ain
Se
le
ct
io
n
AI
Ca
lib
rati
on
Se
le
ct
MUX
CH0
16-Bit 250KS/s
ADC
PGA
MUX
CH1
16-Bit 250KS/s
ADC
PGA
MUX
CH1
16-Bit 250KS/s
ADC
PGA
MUX
CH1
16-Bit 250KS/s
ADC
PGA
MUX
CH0
16-Bit 250KS/s
ADC
PGA
MUX
CH1
16-Bit 250KS/s
ADC
PGA
MUX
CH1
16-Bit 250KS/s
ADC
PGA
MUX
CH0~CH7
16-Bit 250KS/s
ADC
PGA
MUX
CH0
16-Bit 250KS/s
ADC
PGA
MUX
CH1
16-Bit 250KS/s
ADC
PGA
MUX
CH1
16-Bit 250KS/s
ADC
PGA
MUX
CH1
16-Bit 250KS/s
ADC
PGA
MUX
CH0
16-Bit 250KS/s
ADC
PGA
MUX
CH1
16-Bit 250KS/s
ADC
PGA
MUX
CH1
16-Bit 250KS/s
ADC
PGA
MUX
CH8~CH15
16-Bit 250KS/s
ADC
PGA
AI0+~AI7+
AI0-~AI7-
AI8+~AI15+
AI8-~AI15-
GPTC
AFI
GPTC
Control
AFI/Trigger/Decicated Trigger
Timing IO
DATA
DATA
CAL
Source