ADLINK PXI-2022 - Manual (Page 51)

Function Block and Operation Theory 43
4.8 General Purpose Timer/Counter Operation
Two independent 16-bit up/down timer/counter are designed
within FPGA for various applications. They have the following fea-
tures:

Count up/down controlled by hardware or software

Programmable counter clock source (internal or external
clock up to 10 MHz)

Programmable gate selection (hardware or software con-
trol)
 Programmable input and output signal polarities (high active
or low active)

Initial Count can be loaded from software

Current count value can be read-back by software without
affecting circuit operation
4.8.1 Timer/Counter Functions Basics
Each timer/counter has three inputs that can be controlled via
hardware or software. They are clock input (GPTC_CLK), gate
input (GPTC_GATE), and up/down control input
(GPTC_UPDOWN). The GPTC_CLK input provides a clock
source input to the timer/counter. Active edges on the GPTC_CLK
input make the counter increment or decrement. The
GPTC_UPDOWN input controls whether the counter counts up or
down. The GPTC_GATE input is a control signal which acts as a
counter enable or a counter trigger signal under different applica-
tions.
The output of timer/counter is GPTC_OUT. After power-up,
GPTC_OUT is pulled high by a pulled-up resister about 10K
ohms. Then GPTC_OUT goes low after the PXI-2020/2022 is ini-
tialized.
All the polarities of input/output signals can be programmed by
software. In this chapter, for easy explanation, all GPTC_CLK,
GPTC_GATE, and GPTC_OUT are assumed to be active high or
rising-edge triggered in the figures.