ADLINK PXI-2022 - Manual (Page 43)

Function Block and Operation Theory 35
4.5.1 DAQ timing signals
The user-controllable internal timing-signals contain: (Please refer
to Section 4.1.4 for the internal timing signal definition)
1. TIMEBASE, providing TIMEBASE for all DAQ opera-
tions, which could be from internal 80MHz oscillator,
EXTTIMEBASE from I/O connector or the
SSI_TIMEBASE (PXI Trigger Bus [5]). Note that the fre-
quency range of the EXTTIMEBASE is 1MHz to 80MHz,
and the EXTTIMEBASE should be TTL-compatible.
2. AD_TRIG, the trigger signal for the A/D operation, which
could come from external digital trigger, internal software
trigger and SSI_AD_TRIG (PXI Trigger Bus [0]). Refer to
Section 4.5 for detailed description.
3. SCAN_START, the signal to start a scan, which would
bring the following ADCONV signals for AD conversion,
and could come from the internal SI_counter, AFI[0] and
SSI_AD_START. This signal is synchronous to the
TIMEBASE. Note that the AFI[0] should be TTL-compat-
ible and the minimum pulse width should be the pulse
width of the TIMEBASE to guarantee correct functional-
ities.
Timing Signal Category Corresponding Functionality
SSI/PXI signals Multiple cards synchronization
AFI signals Control PXI-2020/2022 by external timing signals
SMB CLK IN Control PXI-2020/2022 by external timing signals
AI_Trig_Out Control external circuitry or boards
Table 4-3: Summary of User-controllable Timing Signals and
Corresponding Functionalities