ADLINK PXI-2022 - Manual (Page 37)

Function Block and Operation Theory 29
an external timebase from the front panel connector AFI[0…7] or
the SMB CLK IN.
As you supply the timebase from external SMB CLK IN, which
should be a sine wave or square wave signal. This signal is AC
coupled with 50Ω input impedance and the valid input level is from
1 to 2 volts peak-to-peak. Note that the external clock should be
continuous for fix sampling rate ADC operation.
4.3.3 External Clock from PXI Interfaces
The PXI-2020/2022 can receive timebase via the PXI Trigger Bus
line 0 by software setting. The eight PXI Trigger Bus lines
(PXI_TRIG[0..7]) provide inter-module synchronization and com-
munication. Note that this function is only available when the PXI-
2020/2022 is in a PXI system. It’s not supported when PXI-2020/
2022 is in a CompactPCI system. When the PXI-2020/2022 is
plugged into a generic peri-pheral slot in a PXI system, it can
receive timebase from PXI_STAR. The PXI_STAR signal comes
from star trigger controller is matched in propagation delay within 1
ns and the delay from star trigger slot to peripheral slot is less than
5 ns. According these hardware features, the PXI-2020/2022 can
achieve very good synchronization performance when using
PXI_STAR as timebase clock source. Note that the function is only
available when the PXI-2020/2022 is in a PXI system. It’s not sup-
ported when the PXI-2020/2022 is in a CompactPCI system.