Altera Active Serial Memory Interface - Manual (Page 27)

Single-Byte Write Operation
This figure shows an example of the latency when the Altera ASMI Parallel IP core is performing a single-
byte write operation.
Figure 11: Writing a Single-Byte
The latency shown does not reflect the true processing time. The latency only shows the command.
Single-byte write operation or when the
PAGE_SIZE
parameter has a value of one does not require
the
shift_bytes
signal. Ensure that the data byte is available on the
datain[7..0]
signal and the
memory address is available on the
addr[23..0]
signal before setting the
write
and
wren
signals
to one.
If
wren
signal has a value of zero, the write operation is not carried out and the
busy
signal
remains deasserted. If the memory region is protected (you can set this in the EPCS/EPCQ/
EPCQ-L status register), then the write operation does not proceed, and the
busy
signal is
deasserted. The IP core then asserts the
illegal_write
signal for two clock cycles to indicate that
the command has been cancelled. The write,
datain[7..0]
, and
addr[23..0]
signals are
registered on the rising edge of the
clkin
signal.
After the IP core receives the write command, it asserts the
busy
signal to indicate that the write
operation is in progress. The
busy
signal stays asserted while the EPCS/EPCQ/EPCQ-L device is
writing the data byte into the flash memory.
Note: If you keep both the
wren
and
write
signals asserted while the
busy
signal is
deasserted after the IP core has finished processing the write command, the IP core
re-registers the
wren
and
write
signals as a value of one and carries out another
write command. Therefore, before the IP core deasserts the
busy
signal, you must
deassert the
wren
and
write
signals.
Note: For EPCQ256 devices, the width of the
addr
and
read_address
signals is 32 bit.
Page-Write Operation
The page-write operation rules are more complicated than the single-byte write operation because you
must shift the data bytes on the
datain[7..0]
signal.
UG-ALT1005
2014.12.15
Single-Byte Write Operation 27
Altera ASMI Parallel IP Core User Guide Altera Corporation
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