Altera Active Serial Memory Interface - Manual (Page 6)

Parameter Legal Values Descriptions
Use ‘read_rdid’ and
‘rdid_out’ ports
—
• Enables the ability to read the memory capacity ID of
the EPCS/EPCQ/EPCQ-L device with an active-high
input signal named
read_rdid
. When this signal is
asserted, the IP core reads the memory capacity ID of
the EPCS/EPCQ/EPCQ-L device. The 8-bit ID appears
on the
rdid_out[7..0]
signal until the device resets.
• This option is available for all devices, except for
EPCS1 and EPCS4.
Enable write operation —
• Enables the ability to write to the EPCS/EPCQ/EPCQ-
L device with an active-high input signal named write.
When this port is asserted, the IP core writes the data
from the
datain[7..0]
signal (for single-byte write) or
from the page-write buffer (for page-write) to the
address that appears on the
addr[23..0]
port, and to
subsequent addresses for page-write. For EPCQ256/
EPCQ-L256 or larger devices, the width of the
addr
and
read_address
signals is 32 bit.
• In page-write mode, you must use the
shift_byte
signal to shift in data bytes before asserting the write
signal.
• This option is available for all EPCS/EPCQ/EPCQ-L
devices.
Use ‘wren’ port —
• Enables write and erase operations to the EPCS/EPCQ/
EPCQ-L memory with an active-high input signal
named
wren
. If this signal is asserted, the write and
erase operations are enabled, and disabled if the signal
is deasserted. If you are not using the
wren
signal, all
write and erase operations are automatically enabled
when the command appears on the relevant IP core
input port. The affected commands are write, sector
protect, bulk erase, and sector erase.
• This option is only available when you turn on the
Enable write operation, Use ‘sector protect’ port or
die erase port, Use ‘bulk erase’ port, or Use ‘sector
erase’ port option.
• This option is available for all EPCS/EPCQ/EPCQ-L
devices.
6 Parameters
UG-ALT1005
2014.12.15
Altera Corporation Altera ASMI Parallel IP Core User Guide
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