Altera Active Serial Memory Interface User Manual
Page 32
Figure 16: Erasing Memory in Bulk
This figure shows an example of the latency when the Altera ASMI Parallel IP core is executing the erase
memory in bulk command. The latency shown does not correctly reflect the true processing time. The
latency only shows the command.
Caution:
This command erases the entire memory on the EPCS/EPCQ/EPCQ_L256 device, including
the configuration data portion. You must use this command with caution.
If the
wren
signal has a value of one, the IP core registers the
bulk_erase
signal at the rising edge
of the
clkin
signal. The IP core asserts the
busy
signal as soon as it receives the
bulk_erase
signal. The
busy
signal remains asserted for as long as it takes to erase the entire EPCS/EPCQ/
EPCQ_L256 memory.
If the
wren
signal has a value of zero, then the IP core will not carry out the
bulk_erase
signal,
and the
busy
signal remains deasserted.
Also, if the memory regions are protected (you can set this in the EPCS/EPCQ/EPCQ_L256 status
register), then the erase operation does not proceed, and the
busy
signal is deasserted. The
illegal_erase
port is then asserted for two clock cycles to indicate that the erase operation has
been cancelled.
Note: If you keep both the
wren
and
bulk_erase
ports asserted while the
busy
signal is
deasserted after the IP core has finished erasing memory in bulk command, the IP
core re-registers the
wren
and
bulk_erase
signals as a value of one and carries out
another bulk erase operation. Therefore, before the IP core deasserts the
busy
signal, you must deassert the
wren
and
bulk_erase
signals. This feature is not
available for EPCQ-L512 and EPCQ-L1024
Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device
Use the
die_erase
signal to instruct the IP core to erase memory in a specified die on the EPCQ-L512 or
EPCQ-L1024 device.
32
Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device
UG-ALT1005
2014.12.15
Altera Corporation
Altera ASMI Parallel IP Core User Guide