Development board setup, Setting up the board, Chapter 4. development board setup – Altera Arria V GT FPGA User Manual

Page 15: Setting up the board –1

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November 2012

Altera Corporation

Arria V GT FPGA Development Kit

User Guide

4. Development Board Setup

The instructions in this chapter explain how to set up the Arria V GT FPGA
development board.

Setting Up the Board

To prepare and apply power to the board, perform the following steps:

1. The Arria V GT FPGA development board ships with its board switches

preconfigured to support the design examples in the kit. If you suspect your board
might not be currently configured with the default settings, follow the instructions
in

“Factory Default Switch and Jumper Settings” on page 4–2

to return the board

to its factory settings before proceeding.

2. The development board ships with design examples stored in the flash memory

device. Verify the Load Selector (SW5.3) is in the on (factory) position to load the
design stored in the factory portion of flash memory.

Figure 4–1

/

Figure 4–2

shows

the switch locations on the Arria V GT FPGA development board.

3. Connect the +19 V, 6.32 A to the DC Power Jack (J6) on the FPGA board and plug

the cord into a power outlet.

c

Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage, and a
lower-rated power supply may not be able to provide enough power for the
board.

4. Set the POWER switch (SW1) to the on position. When power is supplied to the

board, blue LED (D1) illuminates indicating that the board has power.

The MAX II device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. The Load Selector (SW5.3) controls which design
to load. When the switch is in the on (factory) position, the PFL loads the design from
the factory portion of flash memory.

1

The kit includes a MAX II design which contains the MAX II PFL megafunction. The
design resides in the <install
dir>
\kits\arriaVGT_5agtfd7kf40_fpga\examples\max2 directory.

When configuration is complete, the Config Done LED (D16) illuminates, signaling
that the Arria V GT device configured successfully.

f

For more information about the PFL megafunction, refer to

Parallel Flash Loader

Megafunction User Guide

.

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