Altera Arria V GT FPGA - Manual (Page 55)

Appendix A: Programming the Flash Memory Device A–5
Restoring the MAX II CPLD to the Factory Settings
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
1 Because two FPGA devices are hard wired in the JTAG chain, and it is possible to
configure Nios II CPU devices on both FPGAs simultaneously,
nios2-flash-programmer
commands may require the --device=<device index> and
--instance=<instance> arguments.
f For more information about the nios2-flash-programmer utility, refer to the Nios II
Flash Programmer User Guide . To ensure that you have the most up-to-date factory
restore files and information about this product, refer to the Arria V GT FPGA
Development Kit page of the Altera website.
Restoring the MAX II CPLD to the Factory Settings
This section describes how to restore the original factory contents to the MAX II CPLD
on the FPGA development board. Make sure you have the Nios II EDS installed, and
perform the following instructions:
1. Set the board switches to the factory default settings described in “Factory Default
Switch and Jumper Settings” on page 4–2 .
2. Launch the Quartus II Programmer.
3. Click Auto Detect.
4. Click Add File and select <install
dir>\kits\arriaVGT_5agtfd7kf40_fpga\factory_recovery\max2.pof.
5. Turn on the Program/Configure option for the added file.
6. Click Start to download the selected configuration file to the MAX II CPLD.
Configuration is complete when the progress bar reaches 100%.
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
Arria V GT FPGA Development Kit page of the Altera
website.