Altera Arria V GT FPGA - Manual (Page 33)

Chapter 6: Board Test System 6–11
Using the Board Test System
November 2012 Altera Corporation Arria V GT FPGA Development Kit
User Guide
■ LF —lowest frequency divide-by-40 data pattern.
1 Settings HF1, HF2, HF3, LF are for transmit observation only.
Error Control
This control displays data errors detected during analysis and allows you to insert
errors:
■ Detected errors —Displays the number of data errors detected in the hardware.
■ Inserted errors —Displays the number of errors inserted into the transmit data
stream.
■ Insert Error —Inserts a one-word error into the transmit data stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
■ Clear —Resets the Detected errors and Inserted errors counters to zeros.
■ Word error rate —Detected word errors/total received words.
Start
The Start control initiates transaction performance analysis.
Stop
The Stop control terminates transaction performance analysis.
Loopback
These controls display current transaction performance analysis information collected
since you last clicked Start:
■ TX and RX performance bars—Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve.
■ Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per
second.