Altera Arria V GT FPGA - Manual (Page 24)

6–2 Chapter 6: Board Test System
Preparing the Board
Arria V GT FPGA Development Kit November 2012 Altera Corporation
User Guide
Several designs are provided to test the major board features. Each design provides
data for one or more tabs in the application. The Configure menu identifies the
appropriate design to download to the FPGA for each tab.
After successful FPGA configuration, the appropriate tab appears and allows you to
exercise the related board features. Highlights appear in the board picture around the
corresponding components.
The Power Monitor button starts the Power Monitor application that measures and
reports current power information for the board. Because the application
communicates over the JTAG bus to the MAX II device, you can measure the power of
any design in the FPGA, including your own designs.
1 To use the Power Monitor GUI, the MAX II device needs to be programmed with the
default factory MAX II design.
1 The Board Test System and Power Monitor share the JTAG bus with other
applications like the Nios II debugger and the SignalTap
® II Embedded Logic
Analyzer. Because the Quartus II programmer uses most of the bandwidth of the
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the
other applications before attempting to reconfigure the FPGA using the Quartus II
Programmer.
Preparing the Board
With the power to the board off, follow these steps:
1. Connect the USB cable to the board.
2. Ensure that the Ethernet patch cord is plugged into the RJ45 connector.
3. Ensure that the development board switches and jumpers are set to the default
positions as shown in the “Factory Default Switch and Jumper Settings” section
starting on page 4–2 .
4. Set the Load Selector (SW5.3) to the off (user) position.
f
For more information about the board’s DIP switch and jumper settings,
refer to the
Arria V GT FPGA Development Board Reference Manual .
5. Turn on the power to the board. The board loads the design stored in the user
hardware 1 portion of flash memory into the FPGA. If your board is still in the
factory configuration, or if you have downloaded a newer version of the Board
Test System to flash memory through the Board Update Portal, the design loads
the GPIO, Ethernet, and flash memory tests.
c
To ensure operating stability, keep the USB cable connected and the board
powered on when running the demonstration application. The application
cannot run correctly unless the USB cable is attached and the board is on.