Registers, Frequency (mhz), Disable – Altera Arria V GT FPGA User Manual

Page 49: Default, Set new frequency

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Chapter 6: Board Test System

6–27

Configuring the FPGA Using the Quartus II Programmer

November 2012

Altera Corporation

Arria V GT FPGA Development Kit

User Guide

Registers

The Registers control shows the current values from the Si570, Si571, and Si5338A
registers.

Frequency (MHz)

This control allows you to change the frequency of the Si570 and Si571, but you cannot
read the value of this clock via the GUI. However, the Si5338A allows you to read the
output frequencies by clicking read, which may take time to read. You may also
change the output frequency to any of the clocks from 0.16 to 710 MHz. Once you
power cycle the board, your settings will be reset to the default values, except for the
Si570 and Si571 devices.

f

For more information about the Si570, and Si571 registers, refer to the Si570/Si571 data
sheet available on the Silicon Labs website (

www.silabs.com

).

Disable

The Si5338A GUI allows you to disable clock outputs if desired.

Read

This control reads the current frequency setting for the Si5338A associated with the
active tab.

Default

This control sets the frequency for the oscillator associated with the active tab back to
its default value. This can also be accomplished by power cycling the board.

Set New Frequency

The Set New Frequency control sets the programmable oscillator frequency for the
selected clock to the value in the Target frequency control. Frequency changes might
take several milliseconds to take effect. You might see glitches on the clock during this
time. Altera recommends resetting the FPGA logic after changing frequencies.

Configuring the FPGA Using the Quartus II Programmer

You can use the Quartus II Programmer to configure the FPGA with a specific .sof.
Before configuring the FPGA, ensure that the Quartus II Programmer and the
USB-Blaster driver are installed on the host computer, the USB cable is connected to
the FPGA development board, power to the board is on, and no other applications
that use the JTAG chain are running.

To configure the Arria V GT FPGA, perform the following steps:

1. Start the Quartus II Programmer.

2. Click Auto Detect to display the devices in the JTAG chain.

3. Click Add File and select the path to the desired .sof.

4. Turn on the Program/Configure option for the added file.

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