Altera QDRII SRAM Controller MegaCore Function - Manual (Page 35)

Altera Corporation MegaCore Version 9.1 3–3
November 2009 QDRII SRAM Controller MegaCore Function User Guide
Functional Description
Resynchronization & Pipeline Logic
Figure 3–3 shows the resynchronization and pipeline logic block
diagram.
Figure 3–3. Resynchronization & Pipeline Logic Block Diagram
Address & Command Pipeline
The optional address and command pipeline pipelines all commands and
addresses by a predefined number of cycles.
Optional
Address &
Command
Pipeline
Optional
Read Data
Pipeline
Optional
Write Data
Pipeline
From Datapath
Capture
Registers To Control
Block
Read FSM
From
Control
Logic
From
Control
Logic
Resynchronization
Resynchronization
Training
Group
Module
Training Group
Modules
Training
Group
Module
Resynchronization
& Pipeline Logic