Altera QDRII SRAM Controller MegaCore Function - Manual (Page 45)

Altera Corporation MegaCore Version 9.1 3–13
November 2009 QDRII SRAM Controller MegaCore Function User Guide
Functional Description
Figure 3–9. Write—Burst of Four (Wide Mode)
Bursts
Bursts are only possible on the Avalon side in the burst of two mode,
where you can transfer data every clock cycle and in bursts of four
(narrow mode). It is not possible in the burst of four (wide mode), because
it takes two QDRII SRAM clock cycles to transfer one Avalon clock cycle
of data.
Figure 3–10 on page 3–14 shows the burst of four (narrow mode). When
two write requests are sent on the Avalon interface at consecutive
addresses, the controller automatically concatenates them and transfers
them to the QDRII SRAM, if the first one is an even address. If more data
is coming in the following cycle, it is also sent straight away, without any
pause.
avl_write
avl_data_wr[35:0]
avl_adr_wr[19:0]
avl_wait_request_wr
system_clk
qdrii_d[17:0]
qdrii_a[19:0]
qdrii_bwsn[1:0]
qdrii_wpsn
01020304 01020304
0001 0001
01 02 03 04 04
0001 0001
00 00
avl_clk
avl_clock_wr