Altera SDI Audio IP Cores - Manual (Page 19)

This figure shows an example of two audio channels, where the channel signal indicates either channel 1 or
channel 2. Each channel has a start of packet and an end of packet signal, which allows the channel interleaving
and de-interleaving.
Figure 3-8: Multiple Audio Channels
sop
eop
data
channel
A D0 A D1 D188 D189 D2 D3 D190 D4 D191 D188 D189 D190 D191 E E
1 2 1 1 2 1 2 2 2 1 1
Start of packet for audio
sample data channel 1
End of packet for audio
sample data channel 1
End of packet for audio
sample data channel 2
Channel signal indicates
audio channel number
Control data Control data
Start of packet for audio
sample data channel 1
Instantiating the SDI Audio IP Cores
You can instantiate the SDI Audio Embed and Audio Extract IP cores in the following ways:
• Instantiate within Qsys with the audio inputs exposed outside Qsys.
• Instantiate within Qsys with the audio inputs exposed as Avalon-ST Audio within Qsy.
As the SDI Audio Embed and Extract IP cores use an Avalon-MM slave interface to access the control
registers, the most convenient way for you to instantiate the components are within Qsys. You are provided
with the component declaration TCL files to support either the ordinary AES audio inputs or the Avalon-
ST audio interface.
• Instantiate directly in RTL with a CPU register interface.
You can instantiate the SDI Audio Embed and Audio Extract IP cores directly in your RTL and drive the
direct control interface signals directly without the accompanying Avalon-MM register interface
• Instantiate the encrypted core directly on RTL with control ports.
Simulating the Testbench
Altera provides a fixed testbench as an example to simulate the SDI Audio cores. Use this testbench to
simulate the SDI Audio Embed and the associated SDI Audio Extract IP cores, and the SDI Clocked Audio
Input and the associated SDI Clocked Audio Output IP cores.
You can obtain the testbench from ip/altera/audio_ip/simulation directory.
To use the testbench with the ModelSim simulator, follow these steps:
1. Open the Quartus II software.
2. On the File menu, click the New Project Wizard.
3. Specify the working directory to ip/altera/audio_ip/simulation/megacore_build, and give a sensible
name for your project and top-level entity.
4. Click Next, and select Stratix IV for the device family.
SDI Audio IP Functional Description Altera Corporation
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2014.06.30