Altera SDI Audio IP Cores - Manual (Page 38)

SD EDP Presence Register
Reports which audio extended data groups are detected in
the SD-SDI stream. RO EDP Present 3:0
Reserved for future use. — Unused 7:4
Error Status Register
Counts up to 15 errors since last reset. Write 1b to any bit
of this field to reset the entire counter to zero. RW Error counter 3:0
Indicates that an error has been detected in the ancillary
packet checksum. This bit stays set until cleared by writing
1b to this register. RW Ancillary CS fail 4
Indicates that an error has been detected in at least one of
the parity fields:
• ancillary packet parity bit
• audio sample parity bit (for SD-SDI)
• AES sample parity bit (for HD-SDI
This bit stays set until cleared by writing 1b to this register.
RW Ancillary parity fail 5
Indicates that an error has been detected in the channel
status CRC. This bit stays set until cleared by writing 1b to
this register. RW Channel status CRC fail 6
Indicates that an error has been detected in the ECRC that
forms part of the HD audio data packet. This bit stays set
until cleared. To clear, write 1b to this register. RW Audio packet ECRC fail 7
FIFO Status Register
Reports the amount of data in either the audio output FIFO
or the Avalon-ST audio FIFO when the optional Avalon-
ST Audio interface is used. RO FIFO fill level 6:0
This register bit goes high if one of the following occurs
(based on the output mode used):
• underflow or overflow of the audio output FIFO
• overflow of the Avalon-ST audio FIFO
This register always goes high at the beginning, so you must
clear the audio FIFO first for the register to indicate
underflow or overflow.
RW Overflow/underflow 7
Clock Status Register
Defines the frequency of the generated audio. RO Offset 4:0
Reserved for future use. — Unused 6:5
Altera Corporation SDI Audio IP Registers
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5-7 SDI Audio Extract Registers
UG-SDI-AUD
2014.06.30