Altera SDI Audio IP Cores User Manual
Page 31
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Description
Direction
Width
Signal
Reset for the Avalon-MM register interface.
Input
[5:0]
reg_base_addr
Transfer size in bytes.
Input
[5:0]
reg_burst_count
Wait request.
Output
[0:0]
reg_waitrequest
Write request.
Input
[7:0]
reg_write
Data to be written to target.
Input
[0:0]
reg_writedata
Read request.
Input
[0:0]
reg_read
Requested read data valid after read latency.
Output
[0:0]
reg_readdatavalid
Data read from target.
Output
[7:0]
reg_readdata
Altera Corporation
SDI Audio IP Interface Signals
4-11
SDI Audio IP Register Interface Signals
UG-SDI-AUD
2014.06.30
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