Altera SDI Audio IP Cores - Manual (Page 21)

4 SDI Audio IP Interface Signals
2014.06.30
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SDI Audio Embed Signals
The following tables list the signals for the SDI Audio Embed IP cores.
This table lists the general input and output signals.
Table 4-1: SDI Audio Embed General Input and Output Signals
Description Direction Width Signal
This signal resets the system. Input [0:0]
reset
This signal provides the frequency reference used when detecting
the difference between video standards using 1 and 1/1.001 clock
rates. If its frequency is 0, the signal only detects either one of the
clock rates.
The core limits the possible frequencies for this signal to 24.576
MHz, 25 MHz, 50 MHz, 100 MHz, and 200 MHz. Set the required
frequency using the Frequency of fix_clk parameter.
Input [0:0]
fix_clk
If you set the Frequency of fix_clk parameter to 0, you must drive
this signal high to detect a video frame rate of 1/1.001 and low to
detect a video frame rate of 1. For other settings of the Frequency
of fix_clk parameter, the core automatically detects these frame
rates and drives this signal low. Input [0:0]
vid_std_rate
The 48 kHz output clock that is synchronous to the video. This
clock signal is only available when you turn on the Frequency Sine
Wave Generator or Include Clock parameter. Output [0:0]
vid_clk48
This table lists the video input and output signals.
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