Sdi clocked audio output registers, Sdi clocked audio output registers -9 – Altera SDI Audio IP Cores User Manual
Page 40
SDI Clocked Audio Output Registers
The following tables list the registers for the SDI Clocked Audio Output IP core.
Table 5-7: SDI Clocked Audio Output Register Map
Name
Bytes Offset
Channel 0 Register
00h
Channel 1 Register
01h
FIFO Status Register
02h
FIFO Reset Register
03h
Table 5-8: SDI Clocked Audio Output Registers
Description
Access
Name
Bit
Channel 0 Register
The user-defined channel number of audio channel 0.
RW
Channel 0
7:0
Channel 1 Register
The user-defined channel number of audio channel 1.
RW
Channel status RAM select
7:0
FIFO Status Register
This sticky bit reports the overflow of the clocked audio
output FIFO.
RO
Active channel
7:0
FIFO Reset Register
Reserved for future use.
WO
Unused
6:0
Resets the clocked audio FIFO.
WO
FIFO reset
7
Altera Corporation
SDI Audio IP Registers
5-9
SDI Clocked Audio Output Registers
UG-SDI-AUD
2014.06.30