Sdi audio clocked input signals, Sdi audio clocked input signals -8 – Altera SDI Audio IP Cores User Manual

Page 28

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Table 4-11: SDI Audio Extract Direct Control Interface Signals

Description

Direction

Width

Signal

Clock for the direct control interface.

Input

[0:0]

reg_clk

This signal does the same function as the audio control register.

Input

[7:0]

audio_control

This signal does the same function as the audio presence register.

Input

[7:0]

audio_presence

This signal does the same function as the audio status register.

Output

[7:0]

audio_status

This signal does the same function as the SD EDP presence register.

Output

[7:0]

sd_edp_presence

This signal does the same function as the error status register.

Output

[7:0]

error_status

Set any bit of this port high for a single cycle of

reg_clk

to clear

the corresponding bit of the

error_status

signal.

Setting any of bits [3:0] high for a clock cycle resets the entire 4-bit
error counter.

Input

[15:0]

error_reset

This signal does the same function as the FIFO status register.

Input

[7:0]

fifo_status

Set high for a single cycle of

reg_clk

to clear the underflow or

overflow field of the

fifo_status

signal.

Input

[7:0]

fifo_reset

This signal does the same function as the clock status register.

Input

[7:0]

clock_status

Channel status RAM address. The contents of the selected address
will be valid on the

csram_data

signal after one cycle of

reg_clk

.

Input

[5:0]

csram_addr

Channel status data. This signal does the same function as the
channel status RAM.

Input

[7:0]

csram_data

Related Information

SDI Audio Extract Registers

on page 5-4

SDI Audio IP Register Interface Signals

on page 4-10

All SDI Audio IP cores use the same register interface signals.

SDI Audio Clocked Input Signals

The following tables list the signals for the SDI Audio Clocked Input IP cores.

This table lists the input and output signals.

Table 4-12: SDI Audio Clocked Input Input and Output Signals

Description

Direction

Width

Signal

Audio input clock.

Input

[0:0]

aes_clk

Audio data enable.

Input

[0:0]

aes_de

SDI Audio IP Interface Signals

Altera Corporation

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SDI Audio Clocked Input Signals

4-8

2014.06.30

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