Artesyn XMCspan Installation and Use (June 2014) - Manual (Page 43)

Functional Description
XMCSPAN Installation and Use (6806800H03C) 43
 ANSI/VITA 39-2003
 ANSI/VITA 42.0-2005
 ANSI/VITA 42.3-2006
5.7 Mezzanine Card Identification
The mezzanine cards can be identified by reading the VPD serial EEPROM. The connector
signals MSCL and MSCA are connected to the I2C bus.
5.8 XMC.3 Support
The XMCspan implements only the primary XMC.3 connector receptacles at locations J15and
J25. Each primary connector uses 16 differential pairs: 8 defined as transmit, and 8 defined as
receive, plus one 100 MHz differential pair for the PCI Express clock reference. A single four-lane
PCI Express interface is connected between each connector and the PEX8533 PCI Express
Switch.
 PEX8533 Port 2 is connected to connector J15.
 PEX8533 Port 10 is connected to connector J25.
The XMC and XMC.3 specification use sideband signals to power, reset, identify, and manage
the XMC card.
5.9 PMC AND PRPMC Support
Each of the two mezzanine card sites has a separate PCI Express-to-PCI/PCI-X Bridge, which is
the Tsi384.
The PCI signaling voltage for the PMC is 3.3 V.
Each of the two mezzanine card sites implements three PMC connectors for 64-bit wide
PCI/PCI-X interface at locations Jn1, Jn2, and Jn3. Each site also implements one PMC connector
for user I/O signals. Both sites support front panel access to the PMC card, and rear panel access
to PMC user I/O via connector Jn4. The PMC sites support 32/64 bit data. In PCI mode, 33 and