Artesyn XMCspan Installation and Use (June 2014) - Manual (Page 44)

Functional Description
XMCSPAN Installation and Use (6806800H03C) 44
66 MHz clocks are supported. In PCIX mode, 66, 100 and 133 MHz clocks are supported. SW1-
6 must be on to enable 133 MHz PCI-X. If it’s off, the maximum speed is 100 MHz PCI-X. The
PMC connectors have the standard PCI/PCI-X configuration signals. When a module is
installed, the Tsi384 configures the clock and mode to the modules capabilities.
5.10 PCI Buses
The XMCspan has various PCI buses. There is one virtual PCI bus in the PEX8533 PCI Express
switch, and two physical PCI/PCI-X buses between the module sites and the Tsi384 bridge.
5.11 TSI384 PCI EXPRESS-TO-PCI/PCI-X Bridge
The Tsi384 is a bridge that allows the migration of legacy PCI and PCI-X bus interfaces to the
new, advanced serial PCI Express interface.
Tsi384 is equipped with a standard but flexible PCI Express port that scales to x1, x2, or x4 lanes
with a maximum of 1 GB per second of throughput per transmit and receive direction. Its PCI-
X interface can operate up to 133 MHz in PCI-X mode, or up to 66 MHz in PCI mode.
On the XMCspan, the Tsi384 is a 4-lane PCI Express interface that is configured in forward
transparent bridge mode, and is connected with the PEX8533 PCI Express Switch.
PEX8533 Port 1 is connected with Tsi384 Bridge for module site 1.
PEX8533 Port 9 is connected with Tsi384 Bridge for module site 2.
5.12 Serial EEPROM For VPD
The XMCspan has an 8 KB dual address serial EEPROM. The EEPROM contains vital product data
(VPD) configuration information, which may include the following information, among others:
 Manufacturer
 Board Revision
 Build Version
 Date of Assembly